11.2 Note that in this case, the voltage drop across the pMOS transistor will be much smaller than the full VDD level, at any time during the low-to-high transition. Hence, the power dissipation is also less (you may use power-meter simulation described in Chapter 6).
We need at least 10 more requests to produce the solution.
0 / 10 have requested this problem solution
The more requests, the faster the answer.