11.5 The nMOS and pMOS transistors in a CMOS inverter have the following parameters:• |VT0...

11.5 The nMOS and pMOS transistors in a CMOS inverter have the following parameters:

• |V_T0| = 1.0 V for both nMOS and pMOS transistors

•λ = 0.0V^-1

•k′_n = 50.0 μA/V²

•k′_p = 20.0 μA/V²

The CMOS inverter is designed with (W/L)_p=20 and (W/L)_n= 10,and its capacitive load is 2pF. It is assumed that the load capacitance includes all parasitic capacitances connected to the drain node.

(a) Calculate the average power dissipation in the inverter when its input signal is a rectangular pulse with 100 ns period which swings between 5 V and 0 V.

(b) Repeat Part (a) for the case when each transistor channel width is exactly twice as that used in (a), but the load capacitance and input signal remain the same.

(c) What observations can you make from the results of part (b) ? Can you explain why the results should be same or different.

(d) Verify your answer using the power meter with SPICE simulation. For SPICE simulation, you can set the parasitic capacitances in drain and source regions to zero by setting AD, AS, PD, PS to zero.