(ROM-based Implementation) Design a schematic for a readonly memory subsystem with the size of 65536 words by 8 bits wide, using 2764 8 K-by-8-bit ROMs.
(a) Use a single 3:8 decoder and inverters.
(b) Use a single 2:4 decoder and inverters. Is there a clever way to make use of the output enable inputs to the ROM as well as the chip select lines?
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