(Non-Gate Logic) The 2:1 multiplexer function has two data inputs A and B, a select control input S, and a single positive- logic output Z that operates as follows. When S is unasserted, input A is gated to the output. When S is asserted, input B is gated to the output Z. Draw schematics that implement the multiplexer function using only the following components:
(a) Inverting tri-state buffers and conventional inverters.
(b) Open-collector NAND gates, conventional inverters, and pull-up resistors.
(c) Repeat parts (a) and (b) for a four-input multiplexer. S1, S0 = 00 gates A to Z; S1, S0= 01 gates B to Z; S1, S0= 10 gates C to Z; S1, S0 = 11 gates D to Z.
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