Create a 4 × 4 × 2 × 2 matrix of worst-case DC noise margins for the following CMOS interf...

Create a 4 × 4 × 2 × 2 matrix of worst-case DC noise margins for the following CMOS interfacing situations: an (HC, HCT, VHC, or VHCT) output driving an (HC, HCT, VHC, or VHCT) input with a (CMOS, TTL) load in the (LOW, HIGH) state; Figure illustrates. (Hints: There are 64 different combinations, but many give identical results. Some combinations yield negative margins.)