(Design Process) Your task is to implement a finite state machine with the following state...

(Design Process) Your task is to implement a finite state machine with the following state diagram. The finite state machine is actually a complex Gray-code counter. The counter has two control inputs, I1 and I0, which determine the next state. The counter’s functional specification is as follows. When I0 = 00, it is a Gray-code up-counter. When I1I0 = 01, it is a Gray-code down-counter. When I1I0 = 10, it is a Gray-code count-by-two. Finally, when I1I0 = 11, the counter holds it current state. The state diagram is shown in Figure 1.

(a) Complete a state transition table, including the next-state bits (Q1 and Q0) and the needed inputs to the two flip-flops (P1 and P0) to obtain that next state.

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(b) Produce the four-variable K-maps for the next-state functions. Obtain the minimized two-level implementation.

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(c) Draw an implementation schematic, using a minimum number of inverters and two-input NAND, NOR, XOR, and XNOR gates. Assume that complements are not available.

Figure 1

State diagram.