5.2 Layout of the resistive-load inverter design.
(a) Draw the layout of the R-load inverter designed in excise problem (5.6) using a polysilicon resistor with sheet resistivity of 25Ω/square and the minimum feature size of 2µm. It should be noted that L stands for the effective channel length which is related to the mask channel length as L=LM + δ - 2LD, where δ (process error) = 0 and LD= 0.25 µm. To save the chip area, one should use the minimum sizes for L and W. Also, the resistor area can be reduced by using the folded layout (snake pattern) of the resistor.
(b) Perform the circuit extraction to get the SPICE input list from the layout.
(c) Run the SPICE program to obtain the DC voltage transfer characteristic (VTC) curve. Plot the VTC and check whether the calculated values in Problem 5.6 match with the SPICE results.
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