10.6 Consider an 8K x 8K SRAM. An 8K x 8K SRAM has 64K (=65536) memory cells and 8 output lines. In the particular SRAM under discussion, 7 address bits go to the row decoder and 6 address bits go to the column decoder. Bit lines are precharged to VDD= 5 V before each read operation. A read operation is complete when the bit line has dischraged by 0.5 V. A memory cell can provide 1.0 mA of pull-down current to discharge the bit line.
(a) Word line resistance is 390 Ω per memory cell. What formula was used to calculate this resistance?
(b) Word line capacitance is 22 fF per memory cell. What formula was used to calculate this capacitance?
(c) Bit line capacitance is 6 fF per memory cell. What formula was used to calculate this capacitance?
(d) Calculate the access time (row delay + column delay) for this SRAM.
(e) Describe the operation and design of the word line decoder and the bit line decoder.
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