10.2 A single-transistor DRAM cell is represented by the following circuit diagram. Thebitline can be precharged to VDD/2 by using a clocked precharge circuit Also theWRITE circuit is assumed here to bring the potential of the bitline to VDD or 0 Vduring the WRITE operation with wordline at VDD. Using the parameter given:
• VT0 = 1.0 V
• γ = 0.3V1/2
• |2φF| = 0.6 V
(a) Find the maximum voltage across the storage capacitor Cs after WRITE-1 operation, i.e., when the bitline is driven to VDD= 5 V.
(b) Assuming zero leakage current in the circuit, find the voltage at the bitline during READ-1 operation after bitline is first precharged to VDD/2.
Figure P10.2
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