Estimate the resistance per mm of a minimum pitch Cu wire for each layer in the Intel 45 nm process described in Table Assume a 10 nm high-resistance barrier layer and negligible dishing.
TABLE Intel 45 nm metal stack
| Layer | t (nm) | w (nm) | s (nm) | pitch (nm) |
| M9 | 7 μm | 17.5 μm | 13 μm | 30.5 μm |
| M8 | 720 | 400 | 410 | 810 |
| M7 | 504 | 280 | 280 | 560 |
| M6 | 324 | 180 | 180 | 360 |
| M5 | 252 | 140 | 140 | 280 |
| M4 | 216 | 120 | 120 | 240 |
| M3 | 144 | 80 | 80 | 160 |
| M2 | 144 | 80 | 80 | 160 |
| M1 | 144 | 80 | 80 | 160 |
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