10.2 A single-transistor DRAM cell is represented by the following circuit diagram. Thebit...

10.2 A single-transistor DRAM cell is represented by the following circuit diagram. Thebitline can be precharged to V_DD/2 by using a clocked precharge circuit Also theWRITE circuit is assumed here to bring the potential of the bitline to V_DD or 0 Vduring the WRITE operation with wordline at V_DD. Using the parameter given:

• V_T0 = 1.0 V

• γ = 0.3V^1/2

• |2φ_F| = 0.6 V

(a) Find the maximum voltage across the storage capacitor C_s after WRITE-1 operation, i.e., when the bitline is driven to V_DD= 5 V.

(b) Assuming zero leakage current in the circuit, find the voltage at the bitline during READ-1 operation after bitline is first precharged to V_DD/2.

Figure P10.2