List the control logic state table entries for the multiple-cycle computer (see Tables 1,...

List the control logic state table entries for the multiple-cycle computer (see Tables 1, 2 and 3) that implement the following register transfer statements. Assume that in all cases the present state is EX0. If an opcode is needed, use a symbolic name based on the problem part—e.g., for part (a),opcode_a.

(a) R3 ← R7 − R2, →EX1. Assume DR = 3, SA = 7, SB = 2.

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(b) R8 ← sr R8, →INF. Assume DR = 5, SB = 5.

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(c) if (Z = 0) then (PC → PC + se AD, → INF) else (PC → PC +1, → INF).

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(d) R6 ← R6, C ← 0, → INF. Assume DR = SA = 6.

Table 1 Control-Word Information for Datapath

Table 2 Control Information for Sequence Control

Table 3 State Table for Illustration of Instructions Having Three or More Cycles