Using Figure as a guide and a “binary decision” on S from FIGURE 25, write a high-level be...

Using Figure as a guide and a “binary decision” on S from FIGURE 25, write a high-level behavior Verilog description for the adder-subtractor in Figure. Compile and simulate your description. Assuming a ripple carry implementation, apply input combinations to your design that will (1) cause all 16 possible input combinations to be applied to the full addcr-subtractor stage for bit 2, and (2) simultaneously cause the carry output of bit 2 to appear at one of your design's outputs. Also, apply combinations that check the carry chain connections between all full adders by demonstrating that a 0 and a 1 can be propagated from C0 to C4.