Using Figure as a guide anda “when-else” on S from Figure, write a high-level behavior VHDL description for the adder-subtractor in Figure (see Figure for details). Compile and simulate your description. Assuming a ripple carry implementation, apply combinations that check out one of the full adder-subtractor stages for all 16 possible input combinations. Also, apply combinations to check the carry chain connections in between the full adders by demonstrating that a 0 and a 1 can be propagated from C0 to C4. Check the overflow signals as well.
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