The plus (+) indicates a more advanced problem and the asterisk (*) indicates that a solut...

The plus (+) indicates a more advanced problem and the asterisk (*) indicates that a solution is available on the Companion Website for the text.

*Give an example of a sequence of program and data memory read addresses that will have a high hit rate for a unified cache and a low hit rate for separate instruction and data caches. Assume that each of the instruction and data caches is two-way set associative with parameters as in Figure. Assume that the unified cache is four-way set associative with parameters as in Figure. Both the instructions and the data are 32-bit words, and the address resolution is to bytes.

Figure Two-Way Set-Associative Cache