Repeat Exercise if the load is 500 rather than 64 and the delay constraint is 30 ι.Exercis...

Repeat Exercise if the load is 500 rather than 64 and the delay constraint is 30 ι.

Exercise

Consider the buffer design problem from Example. If the delay constraint is 20 ι, how many stages will give the lowest energy, and how should the stages be sized?

Example

A control unit generates a signal from a unit-sized inverter. The signal must drive unit-sized loads in each bitslice of a 64-bit datapath. The designer can add inverters to buffer the signal to drive the large load. Assuming polarity of the signal does not matter, what is the best number of inverters to add and what delay can be achieved?

SOLUTION: Figure shows the cases of adding 0, 1, 2, or 3 inverters. The path electrical effort is H = 64. The path logical effort is G = 1, independent of the number of inverters. Thus, the path effort is F = 64. The inverter sizes are chosen to achieve equal stage effort. The total delay is

The 3-stage design is fastest and far superior to a single stage. If an even number of inversions were required, the two- or four-stage designs are promising. The four-stage design is slightly faster, but the two-stage design requires significantly less area and power

FIGURE Comparison of different number of stages of buffers