Question

6. (20') Asynchronous Counters (Please show all your steps.) (a) How many Flip-flops are required to build a binary counter that counts from 0 to 63? (b) Determine the frequency at the output of the last Flip-flop of this counter for an input clock frequency of 256 KHz. (C) If the counter is initially at zero, what count will it hold after 68 pulses? (d) Suppose the counter was designed to be an asynchronous/ripple counter. Determine the maximum input clock frequency for this counter if tpd for each FF is 50 ns.

Answer 1

(a) The number of Flip Flops n is to be selected such that the number of states (N)   .

N<2n

With n Flip Flop. the largest count possible is   therefor

2n - 1

Minimum number of flip flops required for counting 0 to 63 is

21 – 1 = 63

2n = 64

n = log264 = log2 26 = 6

So 6 Flip Flops are required to build a binary counter that counts 0 to 63.

(b)

If the input clock frequency is f_C then the frequency at the last flip flop is

Where f_C is the clock frequency

n=number of flip flops

fc 256 256 to = 2n = 26 = 64 = 4 KHz

So if the input clock frequency is 256 kHz then the output frequency at the last flip flop is 4 kHz.

(c)

We show a table for the states:

In this counter, we have used 6 flip flops so the total number of states is 64. States start from 0 and end at 63. After 64 pulses, the counter goes into reset states that is 000000 and states after the 68 pulses 000100

Pulse	States	Counts
0	000000	0
1	000001	1
2	000010	2
3	000011	3
........	......	....
62	111110	62
63	111111	63
64	000000	0
65	000001	1
66	000010	2
67	000011	3
68	000100	4

So that after 68 pulses the counter goes at 000100 states.

(d) If we designed to be an asynchronous/ ripple counter then find the maximum input clock frequency if t_pd of each flip flop is 50ns.

Let us: f is the maximum input clock frequency, n is the number of flip flops required to design a ripple counter and t_pd is the propagation delay of each flip flop then

Maximum input clock frequency f = = ntpd

1 Maximum input clock frequency f =- ntpd 6 x 50 x 10-9

109 300 10 X 106 -= 3.33 X 10 Hz = 3.33 MHz 3

So the maximum input clock frequency is 3.33 MHz.