Question

D Flip-Flops

1. Include the symbol and characteristic table of a 1-bit rising edge D flip-flop
2. Write a Verilog module called dflipflop to implement a simple one-bit D flip Flop with input of data and clock and 1-bit output data

Answer 1

Solution :-

DFF Block Diagram is shown below:-

data in data_out reset clock

Truth Table for 1 bit DFF:-

Input Output reset clock 0 1

Verilog code for 1 bit DFF is mentioned below:-

//DFF module
module dff (
input clk, // Clock Input
input rst, // Reset Input
input data_in, // Input Data
output reg data_out // Output Data
);

always @ (posedge clk) // triggers at the postive edge of the clock
begin
if (rst) // Synchronous Active High reset
data_out <= 1'b0;
else
data_out <= data_in; // When reset is not present then it forward the input data to output
end

endmodule