Answer a
=>
=>
=>
Answer b
Clock Rate (CR) = 1/CCT
Ec = IC * CPI
Es = IC * CPI * CCT
Problem 4 (15pts): (a) (5pts) Consider the following MIPS memory with data shown in hex, which...
Problem 4 (15pts): hines iom address oing MIPS memory with data shown in hex, which are located in little-endian byte on rough 15. Show the result of the MIPS instruction "w Ss0, 4(Sa0)" for an byte orders, where $a0 4 Address Contents Address Contents 0a 1 b 2c 3d 8a 9b 10 b4 c5 6d 7e 8f 5f 13 14 15 70 (b) (10pts)Ass specified units. ume we have the following time, performance and architecture parameters in the Ec execution...
Problem 4 (15pts): (a) (5pts) Consider the following MIPS memory with data shown in hex, which are located in memory from address 0 through 15. Show the result of the MIPS instruction "lw Ss0,4(Sa0)" for machines in little-endian byte orders, where Sa0 4. Address Contents Address Contents 9b lb 2 4 6 10 b4 c5 12 13 14 15 3d 5f 70 7 8f (b) (10pts)Assume we have the following time, performance and architecture parameters in the specified units Ec-...
Problem 4 (15pts): (a) (5pts) Consider the following MIPS memory with data shown in hex, which are located in memory from address 0 through 15. Show the result of the MIPS instruction "lw Ss0,4(Sa0)" for machines in little-endian byte orders, where Sa0 4. Address Contents Address Contents 9b lb 2 4 6 10 b4 c5 12 13 14 15 3d 5f 70 7 8f (b) (10pts)Assume we have the following time, performance and architecture parameters in the specified units Ec-...
Topics 1. MIPS instruction set architecture (ISA). 2. Performance. 3. MIPS datapath and control. Exercise 1 Consider the memory and register contents shown below. Registers Ox0100 FFF8 13 ($t 5) 14 ($t6) 0x0100 FFFC 0x0101 0000 Memory 0x0000 0000 0x0001 1100 0x0A00 со00 0x1234 4321 OxBAOO OOBB 15 OXAAAA 0000 0x1111 1010 0x7FFF FFFD 0x0100 FFFO 0x0101 0008 (St7) Ox0101 0004 16 ($80) 0x0101 0008 17 ($sl) Show what changes and give the new values in hexadecimal after the following...
Make sure to show how you solved the problem step-by-step: Consider three different processors P1, P2, and P3, executing the same instruction set. P1 has a clock cycle time of 300 picosecond and a CPI (clock cycles per instruction) of 1.5. P2 has a clock cycle time of 400 picosecond and a CPI of 1.0. P3 has a clock cycle time of 250 picosecond and a CPI of 2.0. P1 is running a program with 10 instructions. P2 is running...
6. Memory Access Time [15 points] Consider a MIPS processor that includes a cache, a main memory, and a hard drive. Access times of cache memory, main memory, and hard drive are 5 ns, 200 ns, and 1000 ns, respectively. Assume that cache memory is divided into instruction cache and data cache. Assume that data cache has a 90% hit rate. Assume that main memory has a 98% hit rate and hard drive is perfect (it has a 100% hit...
Problem 3. (25 pts.) Compilers can have a profound impact on the performance of an application. Assume that for a program, compiler A results in a dynamic instruction count of 1 billion instructions and has an execution time of 1.1 seconds, while compiler B results in a dynamic instruction count of 1.2 billion instructions and an execution time of 1.5 seconds. A) Find the average CPI for each program given that the processor has a clock cycle time of 1...
(e) Suppose we measure the code for the same program from two different compilers and obtain the following data. Assume clock rate is 3GHz, which code sequence will execute faster according to execution time? or According to MIPS? By how much? (25 pts CPI for Instructions Code from Instruction Count (billions) CPI Compiler 1 Compiler 2 9 1 3 (e) Suppose we measure the code for the same program from two different compilers and obtain the following data. Assume clock...
Consider the implemented of two different processors P1, and P2 with the same instruction set architecture (ISA). P1 has a 2 GHZ clock rate and P2 has a 2.5 GHz clock rate. a. what is the clock cycle for each processor? b. If the CPI for a program A is 2, which processor has the highest performance? c. if the processors P1 execute the program in 2 seconds, find the number of instructions. d. We are trying to reduce the...
1. Given the following instruction sequence for the MIPS processor with the standard 5 stage pipeline $10, S0. 4 addi lw S2.0(S10) add sw S2,4(510) $2, $2, $2 Show the data dependences between the instructions above by drawing arrows between dependent instructions (only show true/data dependencies). a. Assuming forwarding support, in what cycle would the store instruction write back to memory? Show the cycle by cycle execution of the instructions as they execute in the pipeline. Also, show any stalls...