1) Explain the value and drawbacks of “non-traditional” hardware architectures for supporting virtual memory (i.e., inverted...
1) Explain the value and drawbacks of “non-traditional” hardware
architectures for supporting virtual memory (i.e., inverted page
table and TLB-only).
2) Using the inverted page table below,
0 | 2 | Process 1
1 | 3 | Process 2
2 | 1 | Process 1
3 | 0 | Process 2
4 | 0 | Process 1
give the physical page frame number corresponding to virtual page
numbers 0, 1, and 2 of Process 1.
Homework Answers
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1) Explain the value and drawbacks of “non-traditional” hardware
architectures for supporting virtual memory (i.e., inverted...
3. Virtual Memory (20 points) An ISA supports an 8 bit, byte-addressable virtual address space. The...
3. Virtual Memory (20 points) An ISA supports an 8 bit, byte-addressable virtual address space. The corresponding physical memory has only 256 bytes. Each page contains 32 bytes. A simple, one-level translation scheme is used and the page table resides in physical memory. The initial contents of the frames of physical memory are shown below. VALUE address size 8 bit byte addressable each byte of addressing type memory has its own address 32 B page size physical memory size 256...
18. You have a byte-addressable virtual memory system with a two-entry TLB, a 2-way set associati...
18. You have a byte-addressable virtual memory system with a two-entry TLB, a 2-way set associative cache, and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16 bytes. In the system below, main memory is divided into blocks, where each block is represented by a letter. Two blocks equal one frame. Given the system state as depicted above, answer the following questions: a) How many bits are in a virtual address...
Question 31 supus Given a computer using a byte-addressable virtual memory system with a two-entry TLB,...
Question 31 supus Given a computer using a byte-addressable virtual memory system with a two-entry TLB, a 2-way set associative cache, and a page table for a process P. Assume cache blocks of size 16 bytes. Assume pages of size 32 bytes and a main memory of 4 frames. Assume the following TLB and page table for Process P: TLB 03 4 هما 0 1 2 3 4 5 6 7 Page Table f Vali d 1 1 0 2...
Main memory has 1,024 bytes, and frames are 32 bits. Assume a portion of main memory,...
Main memory has 1,024 bytes, and frames are 32
bits. Assume a portion of main memory, and the page table,
shown below. The frame numbers in the Page Table are shown as base
10, but all other data in the tables is either binary or hex. A TLB
is not used. The virtual address space for each process is 8 pages.
The first frame in memory is frame 0, but only a portion of memory
is shown (not necessarily that...
Question 1 Which of the following is true about virtual addresses? Virtual addresses for the same...
Question 1 Which of the following is true about virtual addresses? Virtual addresses for the same physical memory location may differ from process to process Virtual addresses are synonymous with physical addresses Virtual addresses always refer to locations on disk Virtual addresses for the same physical memory location may differ from thread to thread Question 2 How do pages and frames relate to each other? A page holds words while a frame holds pictures A frame is a larger structure...
1) Given a virtual memory system with: virtual address 36 bits physical address 32 bits 32KB...
1) Given a virtual memory system with: virtual address 36 bits physical address 32 bits 32KB pages (15 bit page offset) Each page table entry has bits for valid, execute, read and dirty (4 bits total) and bits for a physical page number. a) How many bits in the page table? (do not answer in bytes!) Three digit accuracy is good enough. The exponent may be either a power of 2 or a power of 10. b) The virtual address...
17. A computer system implements a paged virtual memory system. Assume a 16-bit virtual address space...
17. A computer system implements a paged virtual memory system. Assume a 16-bit virtual address space and a 24-bit physical address space. Assume that the first 6 bits of a virtual address index the page table and the rest of the bits are the page offset. A process has the following indexed page table. Index Page Table Entry (PTE) 0x3800 0x3600 0x3200 0x1000 2 3 Each page table entry qives a hexadecimal page frame addresses. Translate the following two hexadecimal...
Exercise l: Suppose that we have a virtual memory space of 28 bytes for a given process and physical memory of 4 page frames. There is no cache. Suppose that pages are 32 bytes in length. 1) How...
Exercise l: Suppose that we have a virtual memory space of 28 bytes for a given process and physical memory of 4 page frames. There is no cache. Suppose that pages are 32 bytes in length. 1) How many bits the virtual address contain? How many bits the physical address contain? bs Suppose now that some pages from the process have been brought into main memory as shown in the following figure: Virtual memory Physical memory Page table Frame #...
3. Assume a virtual memory system with the following properties: • The physical memory available to...
3. Assume a virtual memory system with the following properties: • The physical memory available to an application consists of four-page frames, with frame numbers 0, 1, 2, and 3. The application has six pages of data in its virtual address space, using page numbers 0, 1, 2, 3, 4, and 5. Build a table showing which frame is used to bring in each page for the following sequences of page references using FIFO, MIN, and LRU as page replacement...
Address Translation Question [8 points] Suppose a computing system uses paging with a logical add...
Address Translation Question
[8 points] Suppose a computing system uses paging with a logical
address of 24 bits and a
physical address of 32 bits. The page size is 4KB. Answer each of
the following. If an answer is a power of 2, you can leave it in
the form of a power of 2. ...
2. [20 points] Memory address translation and TLB performance [8 points] Suppose a computing system uses paging with a logical address of 24 bits...
3. Virtual Memory (20 points) An ISA supports an 8 bit, byte-addressable virtual address space. The corresponding physical memory has only 256 bytes. Each page contains 32 bytes. A simple, one-level translation scheme is used and the page table resides in physical memory. The initial contents of the frames of physical memory are shown below. VALUE address size 8 bit byte addressable each byte of addressing type memory has its own address 32 B page size physical memory size 256...
18. You have a byte-addressable virtual memory system with a two-entry TLB, a 2-way set associative cache, and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16 bytes. In the system below, main memory is divided into blocks, where each block is represented by a letter. Two blocks equal one frame. Given the system state as depicted above, answer the following questions: a) How many bits are in a virtual address...
Question 31 supus Given a computer using a byte-addressable virtual memory system with a two-entry TLB, a 2-way set associative cache, and a page table for a process P. Assume cache blocks of size 16 bytes. Assume pages of size 32 bytes and a main memory of 4 frames. Assume the following TLB and page table for Process P: TLB 03 4 هما 0 1 2 3 4 5 6 7 Page Table f Vali d 1 1 0 2...
Main memory has 1,024 bytes, and frames are 32
bits. Assume a portion of main memory, and the page table,
shown below. The frame numbers in the Page Table are shown as base
10, but all other data in the tables is either binary or hex. A TLB
is not used. The virtual address space for each process is 8 pages.
The first frame in memory is frame 0, but only a portion of memory
is shown (not necessarily that...
Question 1 Which of the following is true about virtual addresses? Virtual addresses for the same physical memory location may differ from process to process Virtual addresses are synonymous with physical addresses Virtual addresses always refer to locations on disk Virtual addresses for the same physical memory location may differ from thread to thread Question 2 How do pages and frames relate to each other? A page holds words while a frame holds pictures A frame is a larger structure...
17. A computer system implements a paged virtual memory system. Assume a 16-bit virtual address space and a 24-bit physical address space. Assume that the first 6 bits of a virtual address index the page table and the rest of the bits are the page offset. A process has the following indexed page table. Index Page Table Entry (PTE) 0x3800 0x3600 0x3200 0x1000 2 3 Each page table entry qives a hexadecimal page frame addresses. Translate the following two hexadecimal...
Exercise l: Suppose that we have a virtual memory space of 28 bytes for a given process and physical memory of 4 page frames. There is no cache. Suppose that pages are 32 bytes in length. 1) How many bits the virtual address contain? How many bits the physical address contain? bs Suppose now that some pages from the process have been brought into main memory as shown in the following figure: Virtual memory Physical memory Page table Frame #...
3. Assume a virtual memory system with the following properties: • The physical memory available to an application consists of four-page frames, with frame numbers 0, 1, 2, and 3. The application has six pages of data in its virtual address space, using page numbers 0, 1, 2, 3, 4, and 5. Build a table showing which frame is used to bring in each page for the following sequences of page references using FIFO, MIN, and LRU as page replacement...
Address Translation Question
[8 points] Suppose a computing system uses paging with a logical
address of 24 bits and a
physical address of 32 bits. The page size is 4KB. Answer each of
the following. If an answer is a power of 2, you can leave it in
the form of a power of 2. ...
2. [20 points] Memory address translation and TLB performance [8 points] Suppose a computing system uses paging with a logical address of 24 bits...
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