a)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decade is
Port ( reset, clock, enable : in STD_LOGIC;
counter_out : out STD_LOGIC_VECTOR (3 downto 0);
max : out STD_LOGIC);
end decade;
architecture arch of decade is
signal reg : STD_LOGIC_VECTOR (3 downto 0):= "0000";
begin
process (clock, reset, enable)
begin
if (reset = '1') then reg <= "0000";
elsif rising_edge (clock) then
if (enable = '1') then
if (reg = "1001") then
reg <= "0000";
else
reg <= reg + "0001";
end if;
end if;
end if;
end process;
counter_out <= reg;
max <= '1' when (reg = "1001") else '0';
end arch;
Simulation on Xilinx ISIM
(b) and (d)
(c)
We use structural modelling. Here code of part (a) question used as component
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cascaded is
Port ( clock, reset, enable : in STD_LOGIC;
COUNTER_OUT0 : out STD_LOGIC_VECTOR (3 downto 0);
COUNTER_OUT1 : out STD_LOGIC_VECTOR (3 downto 0);
max : out STD_LOGIC);
end cascaded;
architecture Behavioral of cascaded is
component decade is
Port ( reset, clock, enable : in STD_LOGIC;
counter_out : out STD_LOGIC_VECTOR (3 downto 0);
max : out STD_LOGIC);
end component;
signal s0, s1 : std_logic;
begin
U0: decade port map (reset, clock, enable, COUNTER_OUT0,
s0);
U1: decade port map (reset, clock, s0, COUNTER_OUT1, s1);
max <= s0 and s1;
end Behavioral;
oint each total Implement decade counter in VHDL (counter that counts from 0 to 9). The...
a. How many s are oquinst to build a binary counter that counts tihom 0 to 102" s Determine he fhroquensy at the outpst of the last FF of this counter for an input clock trequneney What is the counter's MOD number? d If the counter is initially at zero, what counter will it hold after 2060 pulses? 9 Cnsider the timing diagram shown below for JK Flip Flop (NOR), Complete the output waveform for Q clock IK Apply the...
how would i draw this circuit The Assignment: Create a second-timer circuit. Decade counters such as 74160 produce four bit binary codes that are BCD codes for the decimal digitals 0 to 9. The chip 7447 can be used to convert a BCD code to the corresponding decimal digit in the form of seven segment signals which can be displayed on a seven segment display unit. You can use two decade counter 74160 chips, each one connects to a 7447...
Design (and then verify your design by simulating it) a two-bit counter that counts up or down. Use an enable input E to determine whether the counter is on or off: if E = 0 the counter is disabled and remains at its present count even if clock pulses are applied. If E = 1, the counter is enabled and a second input, x, determines the direction of the count: if x = 1 the circuit counts upward 00, 01,...
It has four output patterns: 000, 001, 0111 Tho Te two control signals e counter counts when it is 1 and the counter pauses when it is 0 e counter "increases" (circulating through 000, 0011, 01, 111 and .....pping around) when it is 1 and go is 1. The counter "decreases" (circulating in a reversed pattern, ie., 1 1 11, 01 11, 0011, 0001, and wrapping around) when it is 0 and g0 is l The circuit can be constructed...
Use a behavioral Verilog model to design a 3-bit fault tolerant up-down counter. For each flip-flop (FF) include asynchronous reset and preset signals. Refer to Example 4.3 on page 160 for an example of a single FF with both reset and preset signals as well as with an enable signal. For this project, you don't need to use FFs with enables. You don't also need not-q (nq) in this assignment. Use active-high signals for reset and present signals. The example...
A retaining wall is to be constructed in a normally consolidated clayey sand deposit in the figure below. Ground water table is lmbelow the bottom of the excavation. A 20 kN/m2 surcharge pressure is applied over a wide area at the ground surface. Assume the wall moves into the excavation. Consider long-tem analysis (as it is usually the more critical analysis in excavation problems). Ignore capillarity as shown 20 kPa Clayey sand T17 kNm Y-20 kNm 5 m c'-10 kPa...