4. Show how to construct a 5 X 32 decoder with four 3 X 8 decoders (with active high enable inputs) and one 2 X 4 decoder.
4. Show how to construct a 5 X 32 decoder with four 3 X 8 decoders...
1. Make a 4 to 16 decoder circuit from 2 to 4 decoders with details of 4 inputs (high), 1 enable (low), and 16 output (high) 2. Make a series of multiplexers 8 to 1 from multiplexers 2 to 1 with details of 8 inputs (high) 3 selector (high), 1 output (high)
Show the design of a 4-to-16 decoder from 2-to-4 decoders only. Each 2-to-4 decoder has an enable line, E. Please use each of the 2-to-4 decoders in block diagram.
Show how to implement a 5x32 decoder using smaller 3x8 and 2x4 decoders shown below. Label the minterms the resulting 5x32 decoder generates given that the inputs are (x, y, z, t, w) in this order. 0 0 1 1 2x4 lo lo 2 3 2 3 1 11 3x8 4 12 5 6 7
Use 3-to-8 lines decoders to achieve the following: (Decoders should have one active-low ENABLE input, active-high binary code inputs, and active-low outputs. You can use additional gates) F = Σ A,B,C,D (2,4,6,14)
Design the circuit for f(A,B,C,D)=ΠM(0,1,4,7,8,12-15),d(2,3,10) using a minimal number of 3-to-8 line decoders and NAND gates (any size). Decoder outputs must be active-low. Also, assume that the decoder has one active-high enable line G0. If you need NOT gates, you must show them in the diagram using NAND gates.
1) The figure shown below shows how four 74xLS138s (3 to 8 Decoder) can be arranged to function as one-of-32 decoder. The decoders are labeled Zo to Z Answer the following: a. Which output will be activated for A 4As A2 Ai Ao 11101 b. What range of input codes will activate Z2? (MSB 123 :1 2 3 123 11 23 74ALS138 74ALS138 74ALS138 74ALS138 012345671 10123'4 5 6 71 10123A 5 6 7| |0123-4 5 6 7 Oni Os
Draw a 4:16 Decoder that has no enable input (so 4 inputs and 16 outputs) using only 3:8 Decoders that have the enable input hardcoded to a 1. No other gates allowed.
Design a 32-input Mux using 8 and 4 input multiplexers. Design 4 to 16 decoder using 3 to 8 decoders. 6.
using five(5),2 to 4 line decoders with active low enable inputs and active low outputs, and a 4 input NAND gate, draw the circuit diagram that implements the following function. F(W,X,Y,Z) = (Z( W'( X'Y +XY')+W(XY+XY')
Design a four-bit combinational circuit 2'scomplementer. (The output generates the 2's complement of the input binary number.) Construct a 5-to-32-line decoder with enable by using 3-to-8 and 2-to-4-line decoders with enables For the decimal-to-BCD encoder given in the text (Slide 33 of chapter 5), assume by error that the 6 input and the 3 input are both HIGH. What is the output code? Is it a valid BCD code? Construct a 16 times 1 multiplexer with 4 times 1 multiplexers....