Question

As taught previously, an arbiter for 8 input bits, arbin[7:0] outputs 8 "1-hot" output bits, arbout[7:0], that indicate the position of a 1 with highest priority. Bits with higher significance i.e arbin[7] has priority over lower order inputs that are 1's. Use only INV, 2-input NAND and 2- input NOR logic gates in your design. The INV has a delay of 2, 2-input NAND has a delay of 3 and the 2-input NOR has a delay of 4. (a) Implement this function using a bit-cell approach (as shown in the notes). Show the design and determine the td and te for the bus, arbout[7:0]. Recall that td corresponds to the longest delay and te corresponds to the shortest delay. (b) Repeat (a) but implement this function with a look-ahead approach (a wide multi-input AND function built as a tree of 2-input NANDs). Show the design and determine the td and te for the bus, arbout[7:0]

This was previously done poorly and incompletely. Thanks in advance!

Answer 1

0 0 o o 0 0 0 0 ttese t, tt y2 =耳尋尋ㄢ

2 and e ealf 7 2

m V 7 2 1%

囲 b Look ahead appsoad s oad. 42 6 L5 4 0

Min delay ニ 14