Question

ECE 275 - DIGITAL DESIGN Question 1: (@) Write VHDL code for a 2-to-1 multiplexer. - (6) Implement - using only the Sunction R= ab h + bch' + eg h + 8 h 2-to-1 multiplexers. Use the 2-to-1 multiplexer VHDL description as a component to write VHDL code for the of Sunction R, from Problem 1 circuit design

Answer 1

(a)

library ieee;
use ieee.std_logic_1164.all;

entity multiplexer2to1 is
   port (   X, Y   : in std_logic;
       SEL   : in std_logic;
       F   : out std_logic
   );
end multiplexer2to1;

architecture arch of multiplexer2to1 is

begin

   F <= (X and (not SEL)) or (Y and SEL);

end arch;

(b)

R=abh + bch tegh+figh 0 ab+be 12 :1 MUX zil MUX SEL 70 2:1 ΜυX egt89

--VHDL Code using component instantiation

library ieee;
use ieee.std_logic_1164.all;

entity functionR is
   port (   a, b, c, e, f, g, h    : in std_logic;
       R           : out std_logic
   );
end functionR;

architecture arch of functionR is

component multiplexer2to1 is
   port (   X, Y   : in std_logic;
       SEL   : in std_logic;
       F   : out std_logic
   );
end component;

signal S1, S2 : std_logic;

begin

UUT0 : multiplexer2to1 port map (a, c, b, S1);
UUT1 : multiplexer2to1 port map (e, f, g, S2);
UUT2 : multiplexer2to1 port map (S1, S2, h, R);

end arch;