Question

Please help write VHDL code for these two circuit below

7. Write VHDL code to implement the FSM described in the state graph below. 0/0 0/0 1/0 0/0 1/0 ifo 1/0

First what is this mean VLSI related software is reuired this is your comment

am asking a simple question write code similar to this question from your website and here is the link similar circuit

https://www.chegg.com/homework-help/questions-and-answers/write-vhdl-code-two-sequential-logic-write-vhdl-code-implement-fsm-described-state-graph---q9819429

Answer 1

library ieee;
use IEEE.std_logic_1164.all;

entity mealy is
port (clk : in std_logic;
reset : in std_logic;
input : in std_logic;
output : out std_logic
);
end mealy;

architecture behavioral of moore is

type state_type is (s0,s1,s2,s3); --type of state machine.
signal current_s,next_s: state_type; --current and next state declaration.

begin

process (clk,reset)
begin
if (reset='1') then
current_s <= s0; --default state on reset.
elsif (rising_edge(clk)) then
current_s <= next_s; --state change.
end if;
end process;

--state machine process.
process (current_s,input)
begin
case current_s is
when s0 => --when current state is "s0"
if(input ='0') then
output <= '0';
next_s <= s1;
else
output <= '0';
next_s <= s0;
end if;

when s1 =>; --when current state is "s1"
if(input ='0') then
output <= '0';
next_s <= s1;
else
output <= '0';
next_s <= s2;
end if;

when s2 => --when current state is "s2"
if(input ='0') then
output <= '0';
next_s <= s3;
else
output <= '0';
next_s <= s1;
end if;

when s3 => --when current state is "s3"
if(input ='0') then
output <= '0';
next_s <= s1;
else
output <= '1';
next_s <= s2;
end if;

end case;
end process;

end behavioral;