Question

Write a VHDL code to implement the circuit function described below.

Student Id : 8123405

Last 4 digits : 3405

6. Write a VHDL code to implement the circuit function described below The circuit is to display the last four digits of your student ID number on a 7-segment display, one digit at a time, triggered by the falling edge of the clock signal DIR: Direction of the display sequence, T-forward, Ό'-reverse. CLK: clock pulse for the display sequence. RST: reset the display counter Vdd ABCDE F G O D DIR RST CLK For example, if your ID number is 1234567, the last four digits are '4', 5', '6', '7', and the circuit is to display '4', '5', '6', 7,'4', '5','6',7"...when DIR '1' and display Code must be well-organized and clearly explained. Write a small test bench code to perform the simulation and verification Submit your VHDL code, test bench code and the simulation waveforms. (15 marks)

Answer 1

---VHDL Code

--We will design a Moore State Machine, with four states
--Each state will output one digit on seven segment display
--last four digit is 3405
--seven segment display shown is of common anode type

library ieee;
use ieee.std_logic_1164.all;

entity circuit_function is

   port (   DIR   : in std_logic;
       CLK   : in std_logic;
       RST   : in std_logic;
       A, B, C, D, E, F, G : out std_logic
   );
end circuit_function;

architecture arch of circuit_function is

type state is (S0, S1, S2, S3);
signal present_state, next_state : state;

signal seg : std_logic_vector(6 downto 0); --represents gfedcba segments

begin

process (CLK)
begin

   if (RST = '1') then
       present_state <= S0;

   else
       if falling_edge (CLK) then
           present_state <= next_state;
       end if;
   end if;

end process;

process (present_state)
begin
   case (present_state) is
       when S0 =>    if (DIR = '1') then
                   next_state <= S1;
               else
                   next_state <= S3;
               end if;
      
       when S1 =>    if (DIR = '1') then
                   next_state <= S2;
               else
                   next_state <= S0;
               end if;

       when S2 =>    if (DIR = '1') then
                   next_state <= S3;
               else
                   next_state <= S1;
               end if;

       when S3 =>    if (DIR = '1') then
                   next_state <= S0;
               else
                   next_state <= S2;
               end if;

       when others =>    next_state <= S0;

   end case;

end process;

seg <=    "0110000" when (present_state = S0) else    --digit 3
   "0011001" when (present_state = S1) else    --digit 4
   "1000000" when (present_state = S2) else   --digit 0
   "0010010" when (present_state = S2);       --digit 5

A <= seg(0);
B <= seg(1);
C <= seg(2);
D <= seg(3);
E <= seg(4);
F <= seg(5);
G <= seg(6);

end arch;

--Testbench

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity circuit_function_tb is
end;

architecture bench of circuit_function_tb is

component circuit_function
   port (   DIR   : in std_logic;
       CLK   : in std_logic;
       RST   : in std_logic;
       A, B, C, D, E, F, G : out std_logic
   );
end component;

signal DIR: std_logic;
signal CLK: std_logic;
signal RST: std_logic;
signal A, B, C, D, E, F, G: std_logic ;

constant clock_period: time := 10 ns;
  
begin

uut: circuit_function port map ( DIR => DIR,
CLK => CLK,
RST => RST,
A => A,
B => B,
C => C,
D => D,
E => E,
F => F,
G => G );

stimulus: process
begin
  
   RST <= '1';
   DIR <= '1';

   wait for 20 ns;
  
   RST <= '0';

   wait for 60 ns;

   DIR <= '0';
  
wait;
end process;

clocking: process
begin

CLK <= '0';
wait for clock_period / 2;
CLK <= '1';
wait for clock_period / 2;
end process;

end;

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Wave File Edit View Add Format Tools Bookmarks Window Help Wave -Default Msgs erart function-t orcuit_function_tb/RST arcuit functon bB arcuit functon bE S0 650655000 ps 40000 0 ps to 211572 ps 1044 PM O Type here to search

Answer 2

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