--VHDL Model
--We will design a Moore State Machine, with four states
--Each state will output one digit on seven segment display
--last four digit is 0729
--seven segment display shown is of common anode type
library ieee;
use ieee.std_logic_1164.all;
entity circuit_function is
port ( DIR : in
std_logic;
CLK : in
std_logic;
RST : in
std_logic;
A, B, C, D, E, F, G : out
std_logic
);
end circuit_function;
architecture arch of circuit_function is
type state is (S0, S1, S2, S3);
signal present_state, next_state : state;
signal seg : std_logic_vector(6 downto 0); --represents gfedcba segments
begin
process (CLK, RST)
begin
if (RST = '1') then
present_state <= S0;
else
if falling_edge (CLK) then
present_state
<= next_state;
end if;
end if;
end process;
process (present_state, DIR)
begin
case (present_state) is
when S0 => if (DIR
= '1') then
next_state <= S1;
else
next_state <= S3;
end if;
when S1 => if (DIR
= '1') then
next_state <= S2;
else
next_state <= S0;
end if;
when S2 => if
(DIR = '1') then
next_state <= S3;
else
next_state <= S1;
end if;
when S3 => if
(DIR = '1') then
next_state <= S0;
else
next_state <= S2;
end if;
when others => next_state <= S0;
end case;
end process;
seg <= "1000000" when (present_state = S0) else
--digit 0
"1111000" when (present_state = S1) else
--digit 7
"0100100" when (present_state = S2) else
--digit 2
"0010000" when (present_state = S3);
--digit 9
A <= seg(0);
B <= seg(1);
C <= seg(2);
D <= seg(3);
E <= seg(4);
F <= seg(5);
G <= seg(6);
end arch;
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--Testbench
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity circuit_function_tb is
end;
architecture bench of circuit_function_tb is
component circuit_function
port ( DIR : in
std_logic;
CLK : in
std_logic;
RST : in
std_logic;
A, B, C, D, E, F, G : out
std_logic
);
end component;
signal DIR: std_logic;
signal CLK: std_logic;
signal RST: std_logic;
signal A, B, C, D, E, F, G: std_logic ;
constant clock_period: time := 10 ns;
begin
uut: circuit_function port map ( DIR => DIR,
CLK => CLK,
RST => RST,
A => A,
B => B,
C => C,
D => D,
E => E,
F => F,
G => G );
stimulus: process
begin
RST <= '1';
DIR <= '1';
wait for 20 ns;
RST <= '0';
wait for 60 ns;
DIR <= '0';
wait;
end process;
clocking: process
begin
CLK <= '0';
wait for clock_period / 2;
CLK <= '1';
wait for clock_period / 2;
end process;
end;
-------------------------------------------------------------------------------------------------------------------------------------------------------
6. Write a VHDL code to implement the circuit function described below. The circuit is to display the last four dig...
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