--VHDL Code
--We will design a Moore State Machine, with four states
--Each state will output one digit on seven segment display
--last four digit is 3416
--seven segment display shown is of common anode type
library ieee;
use ieee.std_logic_1164.all;
entity circuit_function is
port ( DIR : in
std_logic;
CLK : in
std_logic;
RST : in
std_logic;
A, B, C, D, E, F, G : out
std_logic
);
end circuit_function;
architecture arch of circuit_function is
type state is (S0, S1, S2, S3);
signal present_state, next_state : state;
signal seg : std_logic_vector(6 downto 0); --represents gfedcba segments
begin
process (CLK)
begin
if (RST = '1') then
present_state <= S0;
elsif falling_edge (CLK) then
present_state <=
next_state;
end if;
end process;
process (present_state)
begin
case (present_state) is
when S0 => seg
<= "0110000"; --digit 3
if (DIR = '1') then
next_state <= S1;
else
next_state <= S3;
end if;
when S1 => seg
<= "0011001"; --digit 4
if (DIR = '1') then
next_state <= S2;
else
next_state <= S0;
end if;
when S2 => seg
<= "1111001"; --digit 1
if (DIR = '1') then
next_state <= S3;
else
next_state <= S1;
end if;
when S3 => seg
<= "0000010"; --digit 6
if (DIR = '1') then
next_state <= S0;
else
next_state <= S2;
end if;
when others => next_state <= S0;
end case;
end process;
A <= seg(0);
B <= seg(1);
C <= seg(2);
D <= seg(3);
E <= seg(4);
F <= seg(5);
G <= seg(6);
end arch;
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--Testbench
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
entity circuit_function_tb is
end;
architecture bench of circuit_function_tb is
component circuit_function
port ( DIR : in
std_logic;
CLK : in
std_logic;
RST : in
std_logic;
A, B, C, D, E, F, G : out
std_logic
);
end component;
signal DIR: std_logic;
signal CLK: std_logic;
signal RST: std_logic;
signal A, B, C, D, E, F, G: std_logic ;
constant clock_period: time := 10 ns;
begin
uut: circuit_function port map ( DIR => DIR,
CLK => CLK,
RST => RST,
A => A,
B => B,
C => C,
D => D,
E => E,
F => F,
G => G );
stimulus: process
begin
RST <= '1';
DIR <= '1';
wait for 20 ns;
RST <= '0';
wait for 60 ns;
DIR <= '0';
wait;
end process;
clocking: process
begin
CLK <= '0';
wait for clock_period / 2;
CLK <= '1';
wait for clock_period / 2;
end process;
end;
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Write a VHDL code to implement the circuit function described below. 6. The circuit is to display the last four digits...
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Write a VHDL code to implement the circuit function described below. Student Id : 8123405 Last 4 digits : 3405 6. Write a VHDL code to implement the circuit function described below The circuit is to display the last four digits of your student ID number on a 7-segment display, one digit at a time, triggered by the falling edge of the clock signal DIR: Direction of the display sequence, T-forward, Ό'-reverse. CLK: clock pulse for the display sequence. RST:...
Lab Description Follow the instructions in the lab tasks below to behaviorially create and simulate a flip-flop. Afterwards, you will create a register and use your ALU from Lab 3 to create an accumulator-based processor. This will act ike a simple processor; the ALU will execute si operations and each result will be stored in the register. In an accumulator, the value of the register will be updated with each operation; the register is used as an input to the...