Question

.For the following circuit, do: RR3R2R, Ro G G3G2G,Go Write structural VHDL code. Create two files: i) flip flop, ii) top file (where you will interconnect the flip flops and the logic gates). Provide a printout. (10 pts) Write a VHDL testbench according to the timing diagram shown below. Complete the timing diagram by simulating your circuit (Behavioral Simulation). The clock frequency must be 100 MHz with 50% duty cycle. Provide a printout. (15 pts) Ro R1 R2 Ro resetn G1 clk resetn 0110 1011 R 0000

Answer 1

(a)

The flip-flop file:

library IEEE;
use IEEE.std_logic_1164.all;

entity flip_flop is
port(
  CLK   : in std_logic;
  D     : in std_logic;
  E     : in std_logic;
  RESET     : in std_logic;
  Q     : out std_logic;
end flip_flop;

architecture rtl of flip_flop is
begin
    PROCESS(CLK)
    begin
      if(CLK='1' and CLK'EVENT) then
          if(RESET='0') then
            Q <= 0;
          elsif(E = '1') then
            Q <= D;
          end if
      end if
    end PROCESS;
end rtl;

The top file:

library IEEE;
use IEEE.std_logic_1164.all;

entity my_circuit is
port(
  CLK   : in std_logic;
  RESET : in std_logic;
  E     : in std_logic;
  m     : in std_logic;
  G     : in std_logic_vector(3 downto 0);
  R     : out std_logic_vector(3 downto 0);
end my_circuit;

architecture structural of my_circuit is

component flip_flop
port(
  CLK   : in std_logic;
  D     : in std_logic;
  E     : in std_logic;
  RESET : in std_logic;
  Q     : out std_logic;
end component

component and_gate
port(
   a : in std_logic;
   b : in std_logic;
   c : out std_logic);
end component;

component xor_gate
port(
   a : in std_logic;
   b : in std_logic;
   c : out std_logic);
end component;

signal flip_flop_1_in : std_logic;
signal flip_flop_2_in : std_logic;
signal flip_flop_3_in : std_logic;
signal flip_flop_4_in : std_logic;

signal and_out_1 : std_logic;
signal and_out_2 : std_logic;
signal and_out_3 : std_logic;
signal and_out_4 : std_logic;

begin

    and1: and_gate port map (a => G(0), b => R(3), c => and_out_1);
    and2: and_gate port map (a => G(1), b => R(3), c => and_out_1);
    and3: and_gate port map (a => G(2), b => R(3), c => and_out_1);
    and4: and_gate port map (a => G(3), b => R(3), c => and_out_1);

    xor1: xor_gate port map (a => m, b => and_out_1, c => flip_flop_1_in);
    xor2: xor_gate port map (a => R(0), b => and_out_2, c => flip_flop_2_in);
    xor3: xor_gate port map (a => R(1), b => and_out_3, c => flip_flop_3_in);
    xor4: xor_gate port map (a => R(2), b => and_out_4, c => flip_flop_4_in);

    flip_flop1: flip_flop port map (CLK => CLK, RESET => RESET, E => E, D => flip_flop_1_in, Q => R(0));
    flip_flop2: flip_flop port map (CLK => CLK, RESET => RESET, E => E, D => flip_flop_2_in, Q => R(1));
    flip_flop3: flip_flop port map (CLK => CLK, RESET => RESET, E => E, D => flip_flop_3_in, Q => R(2));
    flip_flop4: flip_flop port map (CLK => CLK, RESET => RESET, E => E, D => flip_flop_4_in, Q => R(3));

end my_circuit;

(b) The test bench code:

The clock frequency is 100 MHz. So the clock period is 10 ns. Since the duty cycle is 50%, the half period is 5 ns;

library IEEE;
use IEEE.std_logic_1164.all;

entity my_circuit_test is
end my_circuit_test;

architecture behavioral of my_circuit_test is

component my_circuit
port(
  CLK   : in std_logic;
  RESET : in std_logic;
  E     : in std_logic;
  m     : in std_logic;
  G     : in std_logic_vector(3 downto 0);
  R     : out std_logic_vector(3 downto 0);
end component

signal CLK : std_logic := '0';
signal RESET : std_logic := '0';
signal E : std_logic := '0';
signal m : std_logic := '0';
signal G : std_logic_vector(3 downto 0) := "1001";
signal R : std_logic_vector(3 downto 0) := (others => '0');

CLK <= not CLK after 5 ns; -- 100 MHz has period of 10 ns. Half period is 5 ns;

begin

    u1: my_circuit port map(
        CLK => CLK,
        RESET => RESET,
        E => E,
        m => m,
        G => G,
        R => R
    )

    tb: PROCESS
    begin
        wait for 10 ns;
        RESET <= '1';
        E <= '1';
        m <= '1';

        wait for 20 ns;
        m <= '0';

        wait for 20 ns;
        E <= '0';
        m <= '1';

        wait for 20 ns;
        E <= '1';
        m <= '0';
        G <= "0110";

        wait for 10 ns;
        E <= '0';

        wait for 10 ns;
        E <= '1';
        m <= '1';

        wait for 10 ns;
        m <= '0';

        wait for 10 ns;
        m <= '1';

        wait for 20 ns;
        E <= '0';

        wait for 10 ns;
        E <= '1';

        wait for 10 ns;
        G <= "1011";

        wait for 10 ns;
        m <= '0';

        wait for 10 ns;
        E <= '0';

    end PROCESS;

end behavioral;