Question

2. For the circuit shown in Figure 4, assume the diode can be modelled by a Constant- Voltage Drop (CVD) (VD[on) = 0.7 V) for d.c analysis. 10 mA 5502 Zc = 0 int) DV D3 D2 V 100 sin(wt) mV vo(t) 1k 12 } 3k 22 Figure 4 (a) Determine the diode d.c current loi, Ioz, 103, Io and V. Check your assumptions. (b) Determine the output ac current, id and voltage, vd (c) Determine the output total current, ip(t) and voltage, vo(t) (7) (4) (2)

Answer 1

0 solna Dc analysis - capacitors open circuited А) Том А 1) t .tv 7 1o, tatlo-ID 0-75 loop VD + Ika 3 kez Applying KVL in loop o SO - (10-ID)(1) - 1.4 +0.7 +3:1) = =(-10-017) + 4.ID = 0 Id=1017 ID3 ID = ID2 = 10-2.675=7.325 mA 2.675 int Now Voc 0-7+ 3k).4.675mA) = 8.725 V . ID = ID2 In = ID3 = ID2 = 7.325 mA = 2.6.75mA Vo= 8.725 v D for analysis at we will model aiode of a resistance given by raz mv | Let mel) IDg

rdi 26m2 V 3-552 7-325 ma & rdz 26 mv 2.675mA = 9.7222 ac equivalent ckt: - Capacitor short circuited De bras Deactivated 5502 siplt > 1 V SS-3 9.721? nmstoluisool USSE Volt) 30002 looon 1007.12 300g.722 i = loosin (wt) = МА 100 sinlwt) (550) +{(1,007.1)113009.73 550 + 754.6 i i = 76.65 Sin(t) MA Now, id 10071 x 76.65 Sin/wt) 1007.1 +3009.7 19.2178 Sin lwt) ut

VYLt) = (d * [3009.72) = 57 84 Sin Lot) my © islayton Tac+do) iolt)= id (²) + ID lolt) =(2-765 mA + 19-2178 Sinkot) ua) Lolt)-[2.765 + UD (t) = Ud (H) + V (57.84 Siniwt) mit 8.725 to v 5xv) 0.0192 Sin(wst)] mA & volt)= (8-725 + 0.05784 Sinet)