Question

Design D Flip Flop show internal circuits using basic gates and 3 inputs data, enable, clock, and one output Q. Show all steps in design.

Answer 1

solution 1 * Designing of D-flipflopo The D-flipflop is by far the most important of the clocked flip flops as it ensures that ensures that inputs sand R are never equal to one at the same time. The D-type flip flop are constructed from a gated SR-flip flop with an inverter added between the sand R inputs to allow for a single D (data) input. Then this single data input, labelled "D" and is used in place of the "set" signal, and the inverter is used to generate the complementary "reset" input there by making a level-sensitive D-type flip flop from an level -sensitive SR latch as now! SED and R. not D as shown as as By eising basic gates D. CIK FF Enable CIK- Enable- Do R Inverter. This is the circuit diagram with basic gates. of D-flipflop

We remember that a simple SR flip-flop requires two inputs, one to "SET" the output and one to "RESET" the output. By connecting an inverter (NOT gate) to the SR flip flop we can SET" and RESET" the flip flop using just one ih pult as now the two input signals are complements of each other. The complement avoid the ambiguity in berent in the SR latch when both inputs are low, since that state is no longer possible. Thus this single input is called as the 'Data" input. If this data input is held HIGH the flip flop would be SET" and when it is the flip flop would change and become "RESET" However, this would be rather pointlers since the output of the flip flop would always change on every pulse applied to this Data input. d. To avoid this an additional inputs called the clock" and Enable input is used to isolate the data input from the flip flop's latching circuitry after the desired data has been stored. The effect is that input condition is only copied the output Q when the LOW Clock input and Enable input is active. This then forms the basis of another sequential device called a "D flip flop! D flip flop" will store and output what ever logic levels as applied data terminal so long as the to its

clock input is HIGH. Once the clock input goes low "set" and "reset" inputs of the flip flop are both beld at logic level "1" so it will not change state and store whatever data was Present on its output before the clock transition occorred. In other words the output is "Latched" at either logic "0" or logic "1" Truth table for the for the D-type flip flops Enable clk Description 0 х memory nochange 1 o Х @ memory no change Reset Q => 0 1 1 set => 1 and here we are using the clock as Positive edge triggered.