Question

2) Complete the following timing diagram for a J-k flip flop with a falling edge trigger and asynchronous CLIN and PreN inputs. CION PreN K Clock

Answer 1

Answer

Consider the Truth table of the JK flip flop with CLrN and PreN inputs,

PreN	ClrN	CLK	J	K		$\bar_Q$
0	0	X	X	X	1	1
0	1	X	X	X	1	0
1	0	X	X	X	0	1
1	1	X	X	X		$\bar_Q$
1	1	$\blacktriangledown$	0	0		$\bar_Q$
1	1	$\blacktriangledown$	0	1	0	1
1	1	$\blacktriangledown$	1	0	1	0
1	1	$\blacktriangledown$	1	1	$\bar_Q$

Timing Diagram Will be

CION PreN J K Clock

Explanation
Considering the above truth table and filling the Timing diagram

1)first transistion

CLrN and PreN are 1,0 respectively,

Without any clk.

Q is 1

2)Second transition,

Falling edge trigger with J =0 and k =1,

So Q = 0,

3)Third transition

Falling edgw with J = 1,K =0,

so Q = 1

4)

CLrN is 0 and PreN is 1,,

so the output Q is 0

5)

Falling Edge Clock with J = 1,K =1 ,

we get Q = Q'

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CION PreN J K Clock