Question

2) Complete the following timing diagram for a J-K flip flop with a falling edge trigger and asynchronous CLrN and PreN inputs. CIN PreN K Clock

Answer 1

Answer

Consider the Truth table of the JK flip flop with CLrN and PreN inputs, with falling edge trigger.

we get the truth table as

JK flipflop Truth Table

PreN	ClrN	CLK	J	K		$\bar_Q$
0	0	X	X	X	1	1
0	1	X	X	X	1	0
1	0	X	X	X	0	1
1	1	X	X	X		$\bar_Q$
1	1	$\blacktriangledown$	0	0		$\bar_Q$
1	1	$\blacktriangledown$	0	1	0	1
1	1	$\blacktriangledown$	1	0	1	0
1	1	$\blacktriangledown$	1	1	$\bar_Q$

With the help of the Above truth table,we can fill the timing diagram as follows.

CION PreN J K Clock

Explanation

1)first transistion

CLrN = 1

PreN = 0

Without any clk.

we get Q is 1

2)For second Second transition,

Falling edge trigger

J =0

k =1,

So Q = 0,

3)For the Third transition

Falling edge with J = 1,

K =0,

so Q = 1

4)Fourth Transition

CLrN is 0 and PreN is 1,,

so the output Q is 0

5)Fith Transistion

Falling Edge Clock

J = 1,

K =1 ,

we get Q = Q'