Question

(25pts) 4. Design a four resistors n-Channel JFET bias circuit for the following specifications: Ip = 3mA, Vps = 7V. Assume: VDD = 14 V, Ipss = 6mA, Vp =- 5V and I = 0 Find Vas and all resistors values. Draw the designed circuit with all calculated values.

Answer 1

© Q) (9 Sol: - Given data ! bias circuit Consider na channel TFET ID=3mA, Ioss = 6 MA VDS: v Vp a -5V VOD - 14V Iq = 0. → NDO. ti4v VID RO R + VDS vas R2 RS VODE +14 I ID fig@ RO Ry = Riller T VDS t vus vs of ug Rs lors= v NG: VDOXR2 fig@ Rot R2

-> K Dow that vus Io : IDIS ] up al 111 j 6 XIV 3x10 5 Vus 17 c 2 vas T 0.707 5 vus 0.3 S Vasa -1.5 V between oavas ? up vases va shompe ܝܐ .. vusa -1.5V 9 loop KUL from figure along apply int that eint vus SA

3 ylis: rIDxes 1.5 Ro 3 3x10 Rs = 0.5k Rs 500 kvL alo along loop → from figure, apply Veo + ID Rot Vost Vs = 0 ID RDA VOD VDS-vs 14-7- 1.5 5.5 IORDE 5.5 2) RD: -3 охо RD = 1.8 uku b. s from from figure 6 VG- VOOX R2 RITR2

Bul- 1.5 V vas vasa lux R2 1.52 Rot R2 R2 0.1074 RITR2 take Rg = lkn . 2 R2 IX10 Rit R2= ㅕ 0.107ly 0.10714 13 x103 RIT R2 9.33 X10 Ri= 8.33Km Ra - lkn Ixn, Rs = 500, RO = 1.84k uz .. R = 8.33 kuh, y from figure @ + VPD fluv RA= 1.84 km Rp = 8.33k2 + VDS = .7V R₂ = 162 Pas 1.51 Rs = 50ou