1.
Let the circuit be labelled as follows :
A = X Y
B = X ' + Y
C = ( ( X ' + Y ) ( X Y ) ) '
Applying De Morgan's law :
C = ( X ' + Y ) ' + ( X Y ) '
Applying De Morgan's law :
C = X Y ' + ( X ' + Y ' )
C = X ' + Y ' + Y ' [ Absorption law ]
C = X ' + Y ' [ Idempotent law ]
So, the output of the given circuit is :
X ' + Y ' .
2.
The sum of product expression from the given truth table is :
F ( x, y, z ) = Σ ( 2, 4, 7 )
= x ' y ' z ' + x y ' z ' + x y z
3.
a)
The expression given is :
( xy ) ' + x ' y '
The circuit for the given expression is :
b)
The expression given is :
( x + y ) ' ( x ' + y )
The circuit for the given expression is :
1. (5 points) Find the output of the given circuit: x х Db 2. (5 points)...
please help me solve these. discrete structures for computing. Answer the following 1) 2points Use a table to express the values of the Boolean function: F(x, y, z) = xy + (xyz) 0 0 0 0 0 1 0 1 0 011 1 0 0 1 0 1 110 11 2) 2points) Find the sum-of-products expansion of the Boolean function: F(x, y, z) = (x + 2)y. i.e. 3) (2 points] Express the Boolean function F(x, y, z) = xy...
Implement the function F (x,y,z)= (not x)(not z)+ xy using a. One 4-to-1 multiplexer and any additional inverters. Show your truth-table and justify your choice of select inputs. b. One 2-to-1 multiplexer and the minimal number of gates. Show the truth table used to derive your circuit.
The state diagram for a sequential circuit in shown below. Input X, Y Output Z 000,D 10/0, 11/0 01/1,11/0 00/0,01/0 01/1,10/1 00/1, 10/0 00/1, 11/1 10/0, 11/1 a) b) c) (4 pts) Find the state table (1 pt) Make a state assignment (3 pts) Find an optimized circuit implementation using SR FFs, NAND gates, and inverters.
part c Problem 3 [10 points a) (5 points) Construct a circuit that takes as input a 3-bit number X-XXXo and increments it by one. L.e. if the input is 101 the output should be 110. Use only half adders. b) Construct a circuit that takes as input a 3-bit number X-XXxo and decrements it by one 1. (5 points) Show the truth table of the circuit. Then use a decoder and additional gates to implement it. So Ys Y2...
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Referring to the circuit in Figure 2 and the corresponding function table in Table 5 on page 5, answer the following questions: a) Draw the state diagram of the circuit (b) (5 Marks) Work out the logic circuit for the Output Block using only NAND gates and inverters. (5 Marks) (c) Give a brief description on the functional characteristics of the circuit in Figure 2 (2 Marks) (d) Redesign the circuit using only one flip-flop and some logic gates. You...
Please solve the problems from 7_8 Digital system please just answer 7_8 thank you 1 Chapter 3 problems 1. Minimize the following Boolean functions into sum-of-products form using a K-majp (a) F(z, y, ;) = Σ(0, 1, 2, 3, 5, 6) (b) F(a,b, c) 20,1,4,5,7) (c) F(z,y,2)s Σ(1.3.5.7) (d) F(a, b, c) 0,4,7) 2. Minimze the following Boolean functions into sum-of-products form using a K-map (b) Fla,b,c)= Π(0.1.4.5.7) (c) F(z, y,z)= Π(2,4,6) (d) F(a,b,c)-Π(1,2,3,4) 3. Minimize the following Boolean functions...
Design a circuit that compares the two-bit integers (x1x0)2 and (y1y0)2, returning an output of 1 when the first 2-bit number is larger and an output of 0 otherwise. a) (3 points) Construct the truth table. b) (4 points) Find the output Boolean function in the canonical sum-of-product format and the canonical product-of-sum format, respectively. c) (4 points) Using K-Map to find the simplified output Boolean function. d) (4 points) Construct the circuit for the obtained Boolean function in part...
2. [20 points] A circuit with 4 inputs has to realize the following 3 functions z, w)-n (0, 1,3,4,9, 11) g (x, y,z, w)-2 (5, 8,9, 10, 11, 12, 13, 14, 15) In what follows the cost a circuit is defined as: Number of gates used + mumber of inputs to these es but not counting NOTs. So, assume that input variables are available in both complemented and un-complemented forms. (a) [10 points] Find simple SOP expressions using K-maps for...
Design a four-bit combinational circuit 2'scomplementer. (The output generates the 2's complement of the input binary number.) Construct a 5-to-32-line decoder with enable by using 3-to-8 and 2-to-4-line decoders with enables For the decimal-to-BCD encoder given in the text (Slide 33 of chapter 5), assume by error that the 6 input and the 3 input are both HIGH. What is the output code? Is it a valid BCD code? Construct a 16 times 1 multiplexer with 4 times 1 multiplexers....