Question

Please carry out prelab design questions

Section Discrete Devices LAB 11 JFET BIAS DESIGN Objective: The objective of this laboratory is to design a JFET amplifier for specific DC operating point, employing self-bias and voltage-divider bias configurations, and verify the accuracy of the design. Prelab: Carry out the following on a separate sheet of paper. Show your work and box answers. 1. Design the self-bias circuit of Figure 11(a) for a centered operating point at /p=4 mA and Vos = 8 V. Use Vp and loss as determined in the previous lab for your JFET, 2. Design the voltage-divider bias circuit of Figure 11(b) for a centered operating point at Ip=4 mA and Vos = 8 V. Stability requirement: Current po should not shift more than 70.5 mA from its original position if the transistor characteristics loss and Vasion change by +25%. VOD VOD RO< Ro HE R13 - MPF102 MPF102 Rs 3 Figure 11(a): Self-bias. Figure 11(b): Voltage-divider bias. Procedure: 1. Breadboard your design of Figure 11(a). Refer to the MPF102 data sheets for pins. 2. Measure and record the following DC voltages and currents. Vpp = _ Vo= ___ Vos = Vos

Answer 1

1) Given that Io = uma , vos= bu from Datasheet Ipss = 20 mA , Up = - BU - let Ves = 150 So, -4.420 > Us Ucs: -4.42 v Now, Vas =- Ip Rs Io = vas! Rs 1-loska 1-4.42 - Rs = uma Rs = 1.105 kr NOW, UDD4Roosurgeo 15-482 - 8 - (4x1.105) = 0 7-4RD -4.42 -0 Ro=0.645ks = 6454 | ºp = 6 5 2 | g=o o idealy RG = 0 . But fort 'Purpose it should be in Megaohm. Practical

2) Given that ... Io = uma , Ups = bu from Datasheet. Inss=20mA, upa. let UDD = 150 - So, Rz 15 ...dj VG = R +Rn from Jp = IDSS (! 4= 20('tooles) → Vas= -4.42 v

NOU - det as = ug -Us -4.42 = UG-IoRs Rs = 1.3km So, ) -4.42 + (443) Now, NDD - IDRo - Uosa Io Rs ao (RD + Rs).4 = 15-6 - Rot Rs = 1.75k So, 0.45k RO 1.75 -1.3 [Ps : 1994 ] now from ew ci) VG - R2 .15 R,+R, let R,= loks So, 0.76= R2 x 15 Tot R2=0.540 kn