Question

Problem: On an ARM processor using big endian format, given the following memory map and [R1] = 0xA10E0C2D, [R2] = 0x00000060, [R3] = 0x00000002, [R4] = 0x0000000C, predict [R1] and [R2] and draw the updated memory map after an ARM data transfer instruction is executed in EACH case. (hint: (1) in this map, each memory location is a word long and occupies 4 bytes; also you only need to draw the section of the memory including the changed word and its address; (2) these instructions are NOT executed one after the other one; instead, each instruction starts with the initial conditions given in the statement.)

0x6C [0x78092A7B]

0x68 [0x56AB8CEF]

0x64 [0x3490AB02]

0x60 [0x902E8C9A]

Instruction:

LDR R1, [R2], #0x4

Answer 1

Given that [R1] = 0xA10E0C2D, [R2] = 0x00000060, [R3] = 0x00000002, [R4] = 0x0000000C

Given that the processor executes in Big Endian format (MSB is stored in the lowest address location), Therefore the address location along with the value is given as follows
0x60 = 0x90
0x61 = 0x2E
0x62 = 0x8C
0x63 = 0x9A
0x64 = 0x34
0x65 = 0x90
0x66 = 0xAB
0x67 = 0x02
0x68 = 0x56
0x69 = 0xAB
0x6A = 0x8C
0x6B = 0xEF
0x6C = 0x78
0x6D = 0x09
0x6E = 0x2A
0x6F = 0x7B

LDR R1,[R2],#0x4
This is in post index notation LDR data:mem[base], #offset
After the execution of this instruction
R1 = 32bit value from address location which is in R2(0x60 - 0x63)
Therefore R1 = 0x902E8C9A
and R2 is added with offset i.e.,0x60+0x04 = 0x64