Question

Number Name 3. Assuming no page fault on a page table access, what is the processor memory access time for the system depicted in the above figure, for a physical memory with 50ns read/write times? 4. Now, assume that the memory system has a translation look-aside buffer (TLB). The TLB requires 10 ns to determine a hit or mess. The physical memory system has an access time of 50ns. You may assume that page fault rate for the application is zero. The TLB hit rate ranges between 0 and 1. For the new system, what must be the TLB hit rate to ensure that the average processor memory access time is no more than one half of the access time calculated in part (b) of this question?

Answer 1

o page size= IK bytes= 20 page orrset= log 2 20 = 10 bit Address spaces 46bytes = 234 bytes Total pages in level 1 = 232 2 = 24 pages size or page Table 2 22 x 2² = 224 bytes > 1 kB Total pages in Level 2 = 224 = 214 pages size of page Table = 24 x 2 = 20 Bytes > 1 kB Total pages in Level 3 = 26 - 26 pages size of page Table = 28 x 2²= 20 cike nverek or entry in 3 pages e dessins [ Ps= cuit | P233 vit pa mit De bonito I P2=8 bit pi=8 bit ID=10bit. oors et P3=6bit I page orrs et ☺ Here at outer level [level-3] page size = 28 Bytes (lessed than 2o Bytes). Here page Tabies do not fill up the whole pagesi 1 entries at a level t Refer of P= Noort page . (px Block size) Bytes memory. I pan entry me partially must be at level- These / Hence LO не" " 1. so that (px Block size ) memory gets wasted

3 physical memory Access Time =50us Number of levels=3 Access time = (Noooo levels t1 ) X MAT = (3+1)x50 = 20ons) TLB TLB bit hate = h access Time=lons n (10+50) +(1-5) x 200 < x200 6on + 200 - 2oon < 100 200 - 1405 <100 1405 > 100 h> 100 140 In> 0.714