3. Consider a paging system with the page table in memory.
A. If a memory reference takes 100 nanoseconds, how long does a paged memory reference take?
B. If we add TLBs, and 75 percent of all page-table references are
found in the TLBs, what is the effective memory
reference time? (Assume that finding a page-table entry for the
TLBs takes 20 nanoseconds.)
C. It takes 750 milliseconds to service a page fault. The page
fault rate is .001. What is the EAT? Include the TLB hit
and miss portions of the equation.
D. What is the purpose of a TLB?
E. What is the purpose of paging?
3. Consider a paging system with the page table in memory. A. If a memory reference takes 100 nanoseconds, how long does...
3. Consider a paging system with the page table in memory. A. If a memory reference takes 100 nanoseconds, how long does a paged memory reference take? B. If we add TLBs, and 75 percent of all page-table references are found in the TLBs, what is the effective memory reference time? (Assume that finding a page-table entry for the TLBs takes 20 nanoseconds.) C. It takes 750 milliseconds to service a page fault. The page fault rate is .001. What...
Problem 3 (25 points): Consider a paging system with the page table stored in memory. Ifa memory reference takes 200 nanoseconds, how long does a paged memory reference take? If we add associative registers, and 75 percent of all page-table references are found in the associative registers, what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time if the entry is there.) a. b.
Q5. Consider a memory system where all pages fit in memory. The TLB takes 15 nanoseconds to access and memory takes 120 nanoseconds to access. What is the effective access time for 1 level paging if the hit rate is 65%? What if it’s 95%? What is the effective access time if not all processes fit into memory and the swap time is 850,000 nanoseconds for a page fault?
Consider a demand-paging system in which the replacement of a page takes 20 milliseconds (access time and data transfer). Addresses are translated through a page table in main memory, with an access time of 1 microsecond per memory access. Thus, each memory reference through the page table takes two accesses. To improve this time, a TLB is added to the system to reduces access time to one memory reference, if the page-table entry is in the associative memory. Assume that...
4. Assume it take 50 nanoseconds to resolve a memory reference when accessing the physical memory address directly. a) We designed a system using virtual addresses with page tables without a TLB. In other words, when fetching data from memory, the page table is accessed to get the PTE for translating an address, a translation is completed, and finally, a memory reference to the desired data is resolved. In this system, what is the effective memory reference time. Assume the...
Question # 3 Consider a demand-paged system where the page table for each process resides in main memory. In addition, there is a fast associative memory (also known as TLB which stands for Translation Look-aside Buffer) to speed up the translation process. Each single memory access takes 1 microsecond while each TLB access takes 0.2 microseconds. Assume that 2% of the page requests lead to page faults, while 98% are hits. On the average, page fault time is 20 milliseconds...
8. (5 points) 10.21 Assume we have a demand-paged memory. The page table is held in registers. It takes 8 milliseconds to service a page fault if an empty page is available or the replaced page is not modified, and 20 if the replaced page is modified. Memory access time is 100 nanoseconds. Assume that the page to be replaced is modified 70 percent of the time. What is the maximum acceptable page- fault rate for an effective access time...
Consider a demand-paging system with a paging disk that has an average access and transfer time of 20 milliseconds. Addresses are translated through a page table in main memory, with an access time of 1 microsecond per memory access. Thus, each memory reference through the page table takes two accesses. To improve this time, we have added an associative memory that reduces access time to one memory reference, if the page-table entry is in the associative memory. Assume that 80...
Please answer the following questions about paged memory... A) How much space needs to be allocated in the minimum and maximum cases for a two-level page table for a machine with a 32-bit virtual memory address, a 1K page size, and which has four times as many inner pages as outer pages? Assume any stored page table value requires 32 bits. B) For the two-level paging approach above, if a Translation Lookaside Buffer (TLB) is used and can cache both...
7 pts Question 30 Consider a computer system that uses virtual memory with paging with a TLB. Suppose main memory access time is 10 ns and the time to look up the TLB 1 ns. Assume no page faults and the TLB has a hit of 95%. What is the effective memory access time (express in ns) 11ns