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Q5. Consider a memory system where all pages fit in memory. The TLB takes 15 nanoseconds...

Q5. Consider a memory system where all pages fit in memory. The TLB takes 15 nanoseconds to access and memory takes 120 nanoseconds to access.

What is the effective access time for 1 level paging if the hit rate is 65%? What if it’s 95%?

What is the effective access time if not all processes fit into memory and the swap time is 850,000 nanoseconds for a page fault?

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