Question

1.We have a single stage, non-pipelined machine and a pipelined machine with 5 pipeline stages. The...

1.We have a single stage, non-pipelined machine and a pipelined machine with 5 pipeline stages. The cycle time of the former is 5 ns and the latter is 1ns.
Assuming no stalls, what is the speedup of the pipelined machine over the single stage machine?

2.We have prediction schemes: not taken, predict taken and dynamic prediction. Which of these prediction would be best if we have no penalty on right, 2 cycles on wrong, average 90% accuracy and 95% frequency

0 0
Add a comment Improve this question Transcribed image text
Request Professional Answer

Request Answer!

We need at least 10 more requests to produce the answer.

0 / 10 have requested this problem solution

The more requests, the faster the answer.

Request! (Login Required)


All students who have requested the answer will be notified once they are available.
Know the answer?
Add Answer to:
1.We have a single stage, non-pipelined machine and a pipelined machine with 5 pipeline stages. The...
Your Answer:

Post as a guest

Your Name:

What's your source?

Earn Coins

Coins can be redeemed for fabulous gifts.

Similar Homework Help Questions
  • A non-pipelined processor has a clock rate of 1 GHz and an average instruction takes 9...

    A non-pipelined processor has a clock rate of 1 GHz and an average instruction takes 9 cycles to execute. The manufacturer has decided to design a pipelined version of this processor. For this purpose, the instruction cycle has been divided into five stages with the following latencies: Stage 1 – 2.0 ns,Stage 2 – 1.5 ns, Stage 3 – 1.0 ns, Stage 4 – 2.6 ns, Stage 5 – 1.9 ns. Each stage will require an extra 0.4 ns for...

  • Suppose that a machine with a 5-stage pipeline uses branch prediction. 12% of the instructions for...

    Suppose that a machine with a 5-stage pipeline uses branch prediction. 12% of the instructions for a given test program are branches, of which 84% are correctly predicted. The other 16% of the branches suffer a 4-cycle mis-prediction penalty. (In other words, when the branch predictor predicts incorrectly, there are four instructions in the pipeline that must be discarded.) Assuming there are no other stalls, develop a formula for the number of cycles it will take to complete n lines...

  • We found that the instruction fetch and memory stages are the critical path of our 5-stage...

    We found that the instruction fetch and memory stages are the critical path of our 5-stage pipelined MIPS CPU. Therefore, we changed the IF and MEM stages to take two cycles while increasing the clock rate. You can assume that the register file is written at the falling edge of the clock. Assume that no pipelining optimizations have been made, and that branch comparisons are made by the ALU. Here’s how our pipeline looks when executing two add instructions: Clock...

  • 1. Suppose we have a 5-stage pipeline CPU and run the following instructions: or $tl, $t2, $t3 or...

    1. Suppose we have a 5-stage pipeline CPU and run the following instructions: or $tl, $t2, $t3 or $t2, $tl, $t4 or $tl, $tl, $t2 1.1. What dependencies are there in the code? 1.2. Suppose there is no forwarding. What hazard may happen? Draw the pipeline diagram and insert stall (nop) to prevent these hazard. 1.3. If the pipeline has full forwarding. Are there still hazard? If so, draw the pipeline diagram and insert stall (nop) to prevent the hazard....

  • We implemented a new 5-stage pipeline with the following features: the delay by data and control...

    We implemented a new 5-stage pipeline with the following features: the delay by data and control hazards are as follows: 1 cycle stall for the load by immediate use, 2 cycle stalls for branch taken. Assume we now run 10,000 instructions on the pipeline, among them: (1) 35% are lw instructions. 10% of lw instructions are followed by instructions that use lw result immediately in ALU input; (2)15% are branch instructions with 40% possibility of branch taken; (3) the remaining...

  • A 5-Stage pipeline is composed of the following stages Instruction Fetch (IF), Decode (DE), Execute (EX), Memory Access...

    A 5-Stage pipeline is composed of the following stages Instruction Fetch (IF), Decode (DE), Execute (EX), Memory Access (ME) and Register Write-back (WB). Assume the pipeline does not have a branch prediction unit, does not have superscalar support and does not support out of order execution. Assume that all memory accesses are in the L1 cache and therefore do not introduce any stalls. Show a pipeline diagram that shows the execution of each stage for the assembly code below. Also...

  • 1. Assume that individual stages of the datapath have the following latencies: IF ID EX MEM...

    1. Assume that individual stages of the datapath have the following latencies: IF ID EX MEM WB 250 ps 350 ps 150 ps 300 ps 200 ps Also, assume that instructions executed by the processor are broken down as follows: alu beq lw sw 45% 20% 20% 15% What is the total latency of an ?w instruction in a pipelined and non-pipelined processor? Instead of a single-cycle organization, we can use a multi-cycle organization where each instruction takes multiple cycles...

  • I need help plz 6. 4-stage MIPS pipeline: It has "IF, ID-EX, MEM, WB" stages. Specify...

    I need help plz 6. 4-stage MIPS pipeline: It has "IF, ID-EX, MEM, WB" stages. Specify how many stalls (or bubbles) are required for the following cases. Assume that there is a forwarding logic and branch condition is determined at ID-EX stage. No delayed branch is assumed. (a) lw $1, 4($0) add $2, $1, $1 (b) lw $1, 4($0) beq $1, $2, add $3, $4, $5 X: sub $3, $3, $5 7. For problem 2 (c), how many bubbles are...

  • In this exercise, we examine how data dependences affect execution in the basic 5-stage pipeline described...

    In this exercise, we examine how data dependences affect execution in the basic 5-stage pipeline described in Section 4.5. Problems in this exercise refer to th following sequence of instructions: addi $2,$2,22 SW $3,20($2) OR $4,$2,$3 Also, assume the following cycle times for each of the options related to forwarding: Without Forwarding With Full Forwarding 300ps With ALU-ALU Forwarding Only 250ps 290ps 4.9.1 [10] <4.5> Indicate dependences and their type. 4.9.2 [10] <S4.5> Assume there is no forwarding in this...

  • Assume that we have the standard 5 stage pipeline from class and the text. Which, if...

    Assume that we have the standard 5 stage pipeline from class and the text. Which, if any, instructions will actively use all 5 stages? Give an example of one. Give an example of an instruction that will use only 4 of the 5 stages -- which stage does the instruction you have given NOT use.

ADVERTISEMENT
Free Homework Help App
Download From Google Play
Scan Your Homework
to Get Instant Free Answers
Need Online Homework Help?
Ask a Question
Get Answers For Free
Most questions answered within 3 hours.
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT