Question

1 pts Design the circuit below to obtain a de voltage of +0.1 V at each of the drains of Q1 and Q2 when vci vG2 0 V. Operate all transistors at Vov 0.31 V and assume that for the process technology in which the circuit is fabricated, Vin-04 V and Cor-400 μA/V2. Neglect channel-length modulation. Determine the W ratio of Qs Voo = +0.9 V RD Ro +0.9 V 2 0.1 mA 0.4 mA -5,--0.9 V
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