Question

2. Domino Logic Sketch the transistor level schematic of a single domino gate that implements the function Y-(A)+ (C-D). The dynamic section of the domino gate should use a foot transistor. (4 points) a) b) Size the transistors so that the dynamic section has the pull-down strength of a unit inverter and the high-skew inverter has the pull-up strength of a unit inverter. (5 points) c) What is the path logical effort G and path parasitic delay P for a rising transition from input to output (that means a falling transition on the intermediate node)? (6 points) d) If the output must drive a load of 500 units of capacitance and the input may present a load of 30 units of capacitance, what is the path effort for a rising transition from input to output (3 points) e) What is the minimum delay (in t) for a rising transition from input to output? (3 points) ) Resize the transistors to achieve this delay. (4 points)

Answer 1