Question

Purpose The purpose of this homework is to better understand how real-world device delays effect the maximum speed of operation in sequential synchronous designs. Assignment A sequential network has been implemented using two D flip/flops, and discrete combinational logic as shown in the figure below. Assume that the inputs A and B always change at the same time as the falling edge of the 50% duty cycle clock. Also assume the following delay parameters for the combinational logic elements: The 4-input OR gate has an inertial delay that ranges from 0.5ns to 3ns, the 3-input OR gate has an inertial delay that ranges from 0.25ns to 2.5ns, the 3-input AND gates have inertial delays that range from 0.25ns to 2ns, the 2-input AND gates have inertial delays that range from 0.25ns to 2.5ns, and the inverting (NOT) gates have inertial delays that range from 0.1ns to 0.5ns. Also assume that the flip-flop propagation delays ranges between, Ins to 3 ns, and their setup time requirement is 0.5ns, and their hold time requirement is 1 ns. HOL 4M Global Cock Enable Reset If there is no clock skew, determine the maximum clock frequency that this design will oper- ate properly and not violate any timing constraints associated with sequential operation. Separately determine if the flip/flop hold time constraints are met.

Answer 1

solutions Values briven in Question: 4-input OR gate inertial Delay = 0.5ns to 3ns 3-input OR gate inertial delay = 0.25ns to 2-5 ng 3 inpet AND gate inestial deddy = 0.25ns to ans 2 input AND gate inertial delay = 0.25ns to 2.Sns NOT gate inestial delay = 0 Ins to 0.5ns ff propagation delay = Ins to ans setup time of FF = 0.5ns. Hold time of FF = Ins Bo ay himen clock skew=0 For proper operation, Mane clock frequency Period> (FF propagation delays + man combination circuit delay ) + (FF sclup time) + (more clock skew) Sman Combination delay path is through I not gate + 3 input AND gate + 4 input or gate = (0.5+ 2+3)ns Ime - 5.5ns

& Period > 3nsts.sns to.sns to ->Period > gns clock skew 8 frequency < gans => foram < 1 + 10 Ha > t < 111•11 MHz. 9 For FF hold time violation to not occurs Hold time é (FF min propagation delay) +(min combinational circuit delay) -(man clock skew) 8 Hold teime a (ff min propagation delay) + ins Ins (min combinational circuit delay) for min combinational delay, the shortest | Path between If output and ff input is 2 input BAND gate + 3 input or gate 1 0.25ns+ 0.25ns - 0.sns. I Ins

For max clock frequency, We first need to calculate minimum period as

Period > ( maximum FF propagation delay) + (max combinational circuit delay) + (FF Setup time) + (max clock skew)

Frequency = [1/(period)]

Hold time constraints specify the amount of time a data input signal should be stable after clock edge. Hold time violations can occur if path length is too short. For hold time violation to not occur

Hold time < (min FF propagation delay) + (min combinational circuit delay) - (max clock skew)