Q1
IN X 5 IS STORED AND IN Y -2 IS STORED
X3=0
X2=1
X1=0
X0=1
Y3=1
Y2=1
Y1=1
Y0=0
AND !ADD/SUB WILL BE 0 BECAUSE WE ARE ADDING TWO BINARY NUMBERS
HENCE ADDING THE TWO WILL GIVE US
S3=0
S2=0
S1=1
S0=1
AND Cn WILL BE 1 AS carry is generated
Q2
IN X 5 IS STORED AND IN Y -2 IS STORED
X3=0
X2=1
X1=0
X0=1
Y3=1
Y2=1
Y1=1
Y0=0
AND !ADD/SUB WILL BE 1 BECAUSE WE ARE Subtracting TWO BINARY NUMBERS
HENCE Subtracting THE TWO WILL GIVE US
S3=0
S2=1
S1=1
S0=1
AND Cn WILL BE 1
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Building and testing basic combinational circuits using Verilog HDL Description: Build and test the following circuits using gate-level modeling in Verilog HDL 1.3-input majority function 2.Conditional inverter (see the table below: x - control input, y -data input). Do NOT use XOR gates for the implementation. Output 3. Two-input multiplexer (see the table below: x.y -data inputs, z- control input) Output 4. 1-bit half adder. 5. 1-bit full adder by cascading two half adders 6.1-bit full adder directly (as in...
Stuoymae Campus 20 pts Question 2 XYo Y) in which inputs X are connect to two 4-bit Design a 4-bit Full Adder with inputs (Xo registers via four 2-to-1 Multiplexers and inputs Y are connected to two other 4-bit registers via four 2-to-1 Multiplexers. In this case assume that Carry in is always zero (and is therefore pull down) and that the register outputs 4-bits at a time. Make sure to show the proper connections between Ful adder, MUXS, and...
Building and testing basic combinational circuits using Verilog HDL Description: Build and test the following circuits using gate-level modeling in Verilog HDL. 1. 3-input majority function. 2. Conditional inverter (see the table below: x - control input, y - data input). Do NOT use XOR gates for the implementation. x y Output 0 y 1 y' 3. Two-input multiplexer (see the table below: x,y - data inputs, z - control input). z Output 0 x 1 y 4. 1-bit half...
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Design a 4-bit Full Adder with inputs (X0...X3, Y0...Y3.), in which inputs X are connect to two 4-bit registers via four 2-to-1 Multiplexers and inputs Y are connected to two other 4-bit registers via four 2-to-1 Multiplexers. In this case, assume that Carry in is always zero (and is therefore pull down) and that the register outputs 4-bits at a time. Please make sure to show the proper connections between Full adder, MUXS, and registers.
Tim Question 1 Atte 20 pts 2H 24 Design a 1-bit Full Adder using NOR gates only, you must include and show: Truth tables, detail logic gate circuit designs, and Boolean expressions Upload Choose a File 20 pts Question 2 Design a 4-bit Full Adder with inputs (Xo...X3, Yo...Y3) in which inputs X are connect to two 4-bit registers via four 2-to-1 Multiplexers and inputs Y are connected to two other 4-bit registers via four 2-to-1 Multiplexers. In this case...
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