Question

Assume the MIPS instruction subset is redefinied to contain only the following instructions:

1. Assume that our MIPS instruction subset is redefined to contain only the following instructions: Instruction Instruction fetch Register read & ALU operation Data Memory Register write decode 0 ns R-format 2ns 1 ns lw ns l ns 2 ns 5 ns 1 ns ns 1 ns ns 0 0 bne The table lists the times required for each step within each instruction. Recall that with the single-cycle and multi-cycle datapaths, the steps with 0 duration are not used. But with the pipeline, every instruction must pass through all 5 pipeline stages. Assume that all registers contain 0 initially. The following instruction sequence is to be executed or $2 $0 $0 and $7 $3.$11 sub $8 $8.$3 sw $5.0x800 ($2) lw $7,0x8040$0) add $8, $8, $8 bne $3, $2, 0x040

Answer 1

a) For 4 R type instructions cycles requried = 4 x 4 = 64
For 1 lw instruction the cycles required is = 5 x 1 = 5
For 1 sw instruction the cycles required is = 4 x 1 = 4
For 1 bne instruction the cycles required is = 3 x 1 = 3

Total clock cycles is = 64+5+5+3 = 77 clock cycles

b) The clock duration is determined by the slowest instruction which is lw in this case with time period = 11ns
hence the clock frequency should be 90.09 Mhz

c) For multicycle datapath the clock frequency is determined by the slowest stage which is of 5ns in this case so the
frequency should be 200 Mhz

d) First instruction will take 5 cycle to pass through all stages (as the pipeline is empty ) then each instruction will be computed in each cycle so total cycles taken is 5+7 = 12 clock cycles