Question

Please help me with this question

Assume the following instruction is to be executed using the 5-cycle pipeline architecture explained in class: LW R1, 500 (R2) Assume Reg[R1] = 16, Reg[R2] = 10, and Mem[510] = 15. Fill out the following table, showing the microinstructions executed and the values of the registers at the end of each pipeline cycle. Use "?" for registers whose values are not known in a cycle. Assume this is the only instruction entering into the pipeline, so no other instructions can affect the outcomes of the registers. Note that each entry of the table carries some points. Points will be deducted for leaving an entry blank Stage Micro.

Answer 1

Hi,

Please find the answer to the question below:-

A1 R1 R2 ALU Output LMD Imm Micro Instructions A 16 16 16 150 150 10 10 10 10 10 2 Stage 2 ID 3 EX 4 MEM S WB 16 16 16 16 10llower 16 bit of instrution register 10llower 16 bit of instrution register 10llower 16 bit of instrution register 10llower 16 bit of instrution register 150 150 10

Instruction fetch cycle Instruction decode/register fetch Execution/Effective address cycle Memory access/branch completion cycle Write-back cycle WHERE IF ID EX MEM WB

=================================================================================

Please let me know in case of any clarification.