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5) Following is a NAND only 1-bit full adder circuit diagram. Using this 1-bit full adder a 128-bit combined addition / subtr

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Answer #1

15 NAND gates are required to implement 1-bit full adder

=> for operating 128-bits of input, we need 128 1-bit full adders

=> 128 * 15 NAND gates

= 1920 NAND gates (1 - to implement 128-bit full adder)

The above circuit will only perform addition operation. In order to support subtraction operation, we need to supply 2's complement of the input as an input to the full adder.

=> the second input has to be complemented for performing subtraction => need to use XOR gate

a mode input, M is used to distinguish between addition and subtraction operation.

if M = 0 => M XOR B => 0 XOR B => B

if M = 1 => M XOR B => 1 XOR B => B'

XOR gate again has to be implemented using 2-input NAND gates. It takes 4 NAND gates to implement one XOR gate

=> 128 * 4 NAND gates

=> 512 NAND gates   (2- to implement 2's complement of second input, B)

Overflow is detected by performing XOR operation on Carry out of 126th full adder, CO127 with Carry out of 127th full adder, CO128

=> required 4 NAND gates to implement one XOR gate

=> 4 NAND gates   (3 - to detect overflow)

Minimum number of NAND gates required to implement 128-bit combined addition/ subtraction circuit with overflow detection = 1920 + 512 + 4

= 2436 NAND gates

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