Question

3- for a direct mapped cache design with a 32 bit address, the following bits of address are used to access the cache Tag Index Offset 31-10 9-5 4-0 a. What is cache block size (in word)? b. How many entries does the cache have? c. What is the ration between total bits required for such a cache implementation one the data storage bits?

Please show your work and answer all parts correctly

Answer 1

Answer:

a)

the offset is from 0 to 4 which means 5 bits

so the block size will be 2^5 = 32 bits

if one word has 8 bits then block size= 4 word

b)

we have bits 5, 6, 7, 8, and 9 for cache entry in the index which is 5 bits

so the number of entries = 2^5= 32 entries

c)

The total bits required for the cache determines the format of the cache implementation and the inside structure determines what kind of cache it is gonna be.

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