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Please help me out with this question. it has two parts, work shown in detail is required so i can understand it

PartA

5.2.3 You are asked to optimize a cache design for the given references. There are three direct-mapped cache designs possible, all with a total of 8 words of data: CI has 1-word blocks, C2 has 2-word blocks, and C3 has 4-word blocks. In terms of miss rate, which cache design is the best? If the miss stall time is 25 cycles, and C1 has an access time of 2 cycles, C2 takes 3 cycles, and C3 takes 5 cycles, which is the best cache design?

PART B

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Answer #1

PART A cache ? : mi/ State-12?100 che:2 missvatt10x 100 total cycles = SX 3?-0.83 1.2 total cycle 25*5? ×100 s- 1 2 113,75 = 114In miss rate way cache 2 is better because less miss rate.

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